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Intel eyes next generation interconnect (video)
After a barage of news from the first day of Intel Developer Forum, it turned out that the chipmaker had been holding back plenty for day two.
In an attempt to counter AMD's Torenza open socket design, Intel said that it had provided Xilinx and Altera with a license that lets them access the front side bus on Intel's processors. This effectively enables a market of application specific co-processors.
But Intel had more in mind. The chipmaker together with IBM unveiled an intiative that aims to build a new interconnect dubbed Geneseo. It pretty much enables the same acceleration devices as providing access to the front side bus, but requires far less openness from Intel.
Below you can watch a video of IBM's Tom Bradicich and Intel's Pat Gelsinger discussing the upcoming standard.
technorati tags: geneseo, intel, ibm, pci-e, interconnect, IDF, gelsinger, bradicich
September 28, 2006 at 05:33 AM | Permalink
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